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INTEGRATED CIRCUITS
DATA SHEET
For a complete data sheet, please also download:
* The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications * The IC06 74HC/HCT/HCU/HCMOS Logic Package Information * The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines
74HC/HCT166 8-bit parallel-in/serial-out shift register
Product specification File under Integrated Circuits, IC06 December 1990
Philips Semiconductors
Product specification
8-bit parallel-in/serial-out shift register
FEATURES * Synchronous parallel-to-serial applications * Synchronous serial data input for easy expansion * Clock enable for "do nothing" mode * Asynchronous master reset * For asynchronous parallel data load see "165" * Output capability: standard * ICC category: MSI GENERAL DESCRIPTION The 74HC/HCT166 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. The 74HC/HCT166 are 8-bit shift registers which have a fully synchronous serial or parallel data entry selected by
74HC/HCT166
an active LOW parallel enable (PE) input. When PE is LOW one set-up time prior to the LOW-to-HIGH clock transition, parallel data is entered into the register. When PE is HIGH, data is entered into the internal bit position Q0 from serial data input (Ds), and the remaining bits are shifted one place to the right (Q0 Q1 Q2, etc.) with each positive-going clock transition. This feature allows parallel-to-serial converter expansion by tying the Q7 output to the Ds input of the succeeding stage. The clock input is a gated-OR structure which allows one input to be used as an active LOW clock enable (CE) input. The pin assignment for the CP and CE inputs is arbitrary and can be reversed for layout convenience. The LOW-to-HIGH transition of input CE should only take place while CP is HIGH for predictable operation. A LOW on the master reset (MR) input overrides all other inputs and clears the register asynchronously, forcing all bit positions to a LOW state.
QUICK REFERENCE DATA GND = 0 V; Tamb = 25 C; tr = tf = 6 ns TYPICAL SYMBOL tPHL/ tPLH PARAMETER propagation delay CP to Q7 MR to Q7 maximum clock frequency input capacitance power dissipation capacitance per package notes 1 and 2 CONDITIONS HC CL = 15 pF; VCC = 5 V 15 14 63 3.5 41 20 19 50 3.5 41 ns ns MHz pF pF HCT UNIT
fmax CI CPD Notes
1. CPD is used to determine the dynamic power dissipation (PD in W): PD = CPD x VCC2 x fi + (CL x VCC2 x fo) where: fi = input frequency in MHz fo = output frequency in MHz (CL x VCC2 x fo) = sum of outputs CL = output load capacitance in pF VCC = supply voltage in V 2. For HC the condition is VI = GND to VCC For HCT the condition is VI = GND to VCC - 1.5 V ORDERING INFORMATION See "74HC/HCT/HCU/HCMOS Logic Package Information".
December 1990
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Philips Semiconductors
Product specification
8-bit parallel-in/serial-out shift register
PIN DESCRIPTION PIN NO. 1 2, 3, 4, 5, 10, 11, 12, 14 6 7 8 9 13 15 16 SYMBOL Ds D0 to D7 CE CP GND MR Q7 PE VCC NAME AND FUNCTION serial data input parallel data inputs clock enable input (active LOW)
74HC/HCT166
clock input (LOW-to-HIGH edge-triggered) ground (0 V) asynchronous master reset (active LOW) serial output from the last stage parallel enable input (active LOW) positive supply voltage
Fig.1 Pin configuration.
Fig.2 Logic symbol.
Fig.3 IEC logic symbol.
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Philips Semiconductors
Product specification
8-bit parallel-in/serial-out shift register
74HC/HCT166
Fig.4 Functional diagram.
FUNCTION TABLE INPUTS OPERATING MODES PE parallel load serial shift hold "do nothing" Notes 1. H = HIGH voltage level h = HIGH voltage level one set-up time prior to the LOW-to-HIGH CP transition L = LOW voltage level I = LOW voltage level one set-up time prior to the LOW-to-HIGH CP transition q = lower case letters indicate the state of the referenced output one set-up time prior to the LOW-to-HIGH CP transition X = don't care = LOW-to-HIGH CP transition I I h h X I I I I h CE X CP X X I h X DS D0-D7 I-I h-h X-X X-X X-X L H L H q0 Qn REGISTER Q0 Q1-Q6 L-L H-H q0 - q5 q0 - q5 q 1 - q6 OUTPUT Q7 L H q6 q6 q7
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Philips Semiconductors
Product specification
8-bit parallel-in/serial-out shift register
74HC/HCT166
Fig.5 Logic diagram.
Fig.6 Typical clear, shift, load, inhibit, and shift sequences.
December 1990
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Philips Semiconductors
Product specification
8-bit parallel-in/serial-out shift register
DC CHARACTERISTICS FOR 74HC For the DC characteristics see "74HC/HCT/HCU/HCMOS Logic Family Specifications". Output capability: standard ICC category: MSI AC CHARACTERISTICS FOR 74HC GND = 0 V; tr = tf = 6 ns; CL = 50 pF Tamb (C) 74HC SYMBOL PARAMETER min. tPHL/ tPLH propagation delay CP to Q7 propagation delay MR to Q7 output transition time +25 typ. 50 18 14 47 17 14 19 7 6 80 16 14 100 20 17 0 0 0 80 16 14 100 20 17 2 2 2 0 0 0 6.0 30 35 17 6 5 25 9 7 -19 -7 -6 14 5 4 33 12 10 -8 -3 -2 -28 -10 -8 19 57 68 -40 to +85 max. min. 150 30 26 160 32 27 75 15 13 100 20 17 125 25 21 0 0 0 100 20 17 125 25 21 2 2 2 0 0 0 4.8 24 28 max. 190 38 33 200 40 34 95 19 16 120 24 20 150 30 26 0 0 0 120 24 20 150 30 26 2 2 2 0 0 0 4.0 20 24 -40 to +125 min. max. 225 45 38 240 48 41 110 22 19 ns
74HC/HCT166
TEST CONDITIONS UNIT VCC (V) 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 WAVEFORMS
Fig.7
tPHL
ns
Fig.8
tTHL/ tTLH
ns
Fig.7
tW
clock pulse width HIGH or LOW master reset pulse width LOW removal time MR to CP set-up time Dn, CE to CP set-up time PE to CP hold time Dn, CE to CP hold time PE to CP maximum clock pulse frequency
ns
Fig.7
tW
ns
Fig.8
trem
ns
Fig.8
tsu
ns
Fig.9
tsu
ns
Fig.8
th
ns
Fig.8
th
ns
Fig.9
fmax
MHz
Fig.7
December 1990
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Philips Semiconductors
Product specification
8-bit parallel-in/serial-out shift register
DC CHARACTERISTICS FOR 74HCT For the DC characteristics see "74HC/HCT/HCU/HCMOS Logic Family Specifications". Output capability: standard ICC category: MSI Note to HCT types
74HC/HCT166
The value of additional quiescent supply current (ICC) for a unit load of 1 is given in the family specifications. To determine ICC per input, multiply this value by the unit load coefficient shown in the table below.
INPUT D0 to D7 Ds CP CE MR PE
UNIT LOAD COEFFICIENT 0.35 0.35 0.80 0.80 0.40 0.60
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Philips Semiconductors
Product specification
8-bit parallel-in/serial-out shift register
AC CHARACTERISTICS FOR 74HCT GND = 0 V; tr = tf = 6 ns; CL = 50 pF Tamb (C) 74HCT SYMBOL PARAMETER min. tPHL/ tPLH tPHL tTHL/ tTLH tW tW trem tsu tsu th th fmax propagation delay CP to Q7 propagation delay MR to Q7 output transition time clock pulse width HIGH or LOW master reset pulse width LOW removal time MR to CP set-up time Dn, CE to CP set-up time PE to CP hold time Dn, CE to CP hold time PE to CP maximum clock pulse width 20 25 0 16 30 +25 typ. 23 22 7 9 11 -7 8 15 -3 -13 45 -40 to +85 max. min. 40 40 15 25 31 0 20 38 max. 50 50 19 30 38 0 24 45 -40 to +125 min. max. 60 60 22 ns ns ns ns ns ns ns ns
74HC/HCT166
TEST CONDITIONS UNIT VCC (V) 4.5 4.5 4.5 4.5 4.5 4.5 4.5 4.5 WAVEFORMS
Fig.7 Fig.8 Fig.7 Fig.7 Fig.8 Fig.8 Fig.9 Fig.8
0 0 25
0 0 20
0 0 17
ns ns MHz
4.5 4.5 4.5
Fig.9 Fig.9 Fig.7
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Philips Semiconductors
Product specification
8-bit parallel-in/serial-out shift register
AC WAVEFORMS
74HC/HCT166
The changing to output assumes internal Q6 opposite state from Q7. The number of clock pulses required between the tPLH and tPHL measurements can be determined from the function table. (1) HC : VM = 50%; VI = GND to VCC. HCT: VM = 1.3V; VI = GND to 3V.
Fig.7
Waveforms showing the clock (CP) to output (Q7) propagation delays, the clock pulse width, the output transition times and the maximum clock frequency.
The number of clock pulses required between the tPLH and tPHL measurements can be determined from the function table. (1) HC : VM = 50%; VI = GND to VCC. HCT: VM = 1.3V; VI = GND to 3V.
Fig.8
Waveforms showing the master reset (MR) pulse width, the master reset to output (Q7) propagation delay and the master reset to clock (CP) removal time.
December 1990
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Philips Semiconductors
Product specification
8-bit parallel-in/serial-out shift register
74HC/HCT166
The number of clock pulses required between the tPLH and tPHL measurements can be determined from the function table. CE may change only from HIGH-to-LOW while CP is LOW. The shaded areas indicate when the input is permitted to change for predictable output performance. (1) HC : VM = 50%; VI = GND to VCC. HCT: VM = 1.3V; VI = GND to 3V.
Fig.9
Waveforms showing the set-up and hold times from the serial data input (Ds), the data inputs (Dn), the clock enable input (LOW CE), the clock enable input CE and the parallel enable input to the clock (CP).
PACKAGE OUTLINES See "74HC/HCT/HCU/HCMOS Logic Package Outlines".
December 1990
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